AMD Ryzen ThreadRipper PRO 7995WX - 2.5 GHz - 96-kjerners - 192 tråder - 384 MB cache - Socket sTR5 - PIB/WOF
FBAC4895-B52C-4E03-B099-A6A8F8B8017B Created with sketchtool. 706D6907-81E1-46A2-B8F9-7B702A1EF2C7 Created with sketchtool. 6A870209-E7F5-44F5-A66F-09E20C85A0DC Created with sketchtool. 0BB04D6C-A9AB-4913-BF4F-5A23954E68E1 Created with sketchtool. 501E26C7-66C1-4DAA-B740-6CFAF55A1B39 Created with sketchtool. C105F7D3-D5EE-43C9-9EE8-05CC42B296D4 Created with sketchtool. D94689D8-7CBB-41C8-AC06-F79D81FF82D5 Created with sketchtool. DA4C7ED9-2512-4D52-94F0-92800F2A6E04 Created with sketchtool. 42E133FD-828F-4CF4-A0BF-560014487A57 Created with sketchtool. F52D9745-4BFD-4506-BEEF-630FD09EF2D9 Created with sketchtool.
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AMD Ryzen Threadripper PRO processor is the first and only professional workstation-caliber CPU to exploit a 7 nm silicon manufacturing process, allowing engineers to double the density and fueling the transistor budget needed to substantially drive-up core throughput. With the unveiling of the first generation of "Zen" CPU technology, AMD disrupted the status quo with a microarchitecture completely rebuilt from the ground up and optimized for modern single and multi-threaded workloads. With the Threadripper PRO processor's "Zen 2" microarchitecture, improvements are many, but two carry most of the weight, especially where high demand professional computing is concerned: up to 15% faster instructions per cycle (IPC), and an impressive quadrupling of the peak floating point throughput rate. The former comes primarily by the way of improved branch prediction and pre-fetching, supported by much deeper and broader allocation of cache, while the latter is the result achieved by both doubling the width of the FPU data path and doubling density. Supporting the increased compute throughput, architects doubled load-store bandwidth and dialed up dispatch and retire bandwidth to minimize the chances the higher throughput ALUs would be starved of data.